The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to an EPROM (Erasable and Programmable Read-Only Memory) or an EEPROM (Electrically Erasable and Programmable Read-Only Memory), and also to a constant-voltage generating circuit for use therein as a bit-line bias circuit.
Generally, in an EPROM and a flash EEPROM, one MOS transistor is connected between a bit-line load circuit and each bit line connected to memory cells, for clamping the bit-line potential at the time of reading data from the memory cells. A bias voltage is applied to the gate of the MOS transistor from a constant-voltage generating circuit. The constant-voltage generating circuit is generally known as "bit-line bias circuit".
FIG. 1 shows the basic structure of a constant-voltage generating circuit which is described in Jpn. Pat. Appln. KOKAI Publication No. 9-082094. All MOS transistors incorporated in this circuit are of enhancement type. Since the circuit has no depletion-type transistors, impurities need not be diffused into the channel region of each transistor to impart a low threshold voltage thereto. Hence, the constant-voltage generating circuit can be manufactured in a fewer steps than otherwise.
As shown in FIG. 1, P-channel MOS (PMOS) transistors P1 and P2, which constitute a current mirror circuit, have their sources connected to a Vdd node. The gates of the transistors P1 and P2 are connected to each other and to the drain of the transistor P1. The drains of the transistors P1 and P2 are connected to the drains of NMOS transistors N1 and N2. The gates of the NMOS transistors N1 and N2 are connected to each other and to the drain of the PMOS transistor P2.
The source of the NMOS transistor N1 is connected to the ground. The source of the NMOS transistor N2 is connected to the node n1 of the gate and drain of an NMOS transistor N3. The source of the NMOS transistor N3 is connected to the ground.
The drain of the PMOS transistor P2 and the gate and drain of the NMOS transistor N2 are connected to one another, forming a node n0. It is from the node n0 that a voltage Vo is output, which will be used as a bias voltage Vbias. The NMOS transistor N1 functions as a constant-current source. The NMOS transistors N2 and N3 constitute a load circuit.
FIG. 2 illustrates the actual structure of the constant-voltage generating circuit.
As shown in FIG. 2, a PMOS transistor P3 is connected between the Vdd node and the PMOS transistor P1, and a PMOS transistor P4 is connected between the Vdd node and the PMOS transistor P2. The PMOS transistor P4 has its gate connected to the ground. The PMOS transistor P3 has its gate connected to receive a control signal SW through an inverter circuit IV.
An NMOS transistor N5 is connected between the ground and the node of the PMOS transistor P1 and the NMOS transistor N1. The NMOS transistor N5 has its gate connected to receive the control signal SW through the inverter circuit IV.
NMOS transistors N6 and N7 are connected, forming a series circuit. The series circuit is connected between the node n0 and the ground. The NMOS transistor N6 has its gate connected to the node n1. The NMOS transistor N7 has its gate connected to receive the control signal SW. The node of the NMOS transistors N6 and N7 is connected to the source of the NMOS transistor N3.
The operation of the circuit shown in FIG. 2 will be described, with reference to FIG. 3 which represents the waveform of the control signal SW and the waveform of the bias voltage Vbias.
When the chip enable signal is inactive, the control signal SW is at low (L) level. The output signal of the inverter circuit IV is at high (H) level. Hence, the PMOS transistor P3 is turned off, whereas the NMOS transistor N5 is turned on. Hence, the PMOS transistor P2 is turned on, too. The NMOS transistor N7, which receives the control signal SW, is turned off. As a result, the NMOS transistors N2, N3 and N6 are turned off. Since the PMOS transistor P2 is on, and the PMOS transistor P4 is always on, the voltage at the node n0, i.e., the bias voltage Vbias, is equal to the power-supply voltage Vdd.
On the other hand, when the chip enable signal is active, the control signal SW is at "H" level. The NMOS transistor N7 is turned on, whereby the NMOS transistors N2, N3 and N6 decrease the potential at the node n0 to the ground potential.
The NMOS transistor N6 serves to decrease the voltage Vbias quickly, or to raise the speed with which the potential at the node n0 changes. Thus, the bias voltage Vbias quickly falls from the power-supply voltage Vdd to the ground potential. Were the NMOS transistor N6 not provided, the potential at the node n0 could not change sufficiently fast.
When the control signal SW rises to "H" level, the output signal of the inverter circuit IV falls to "L" level. As a result, the PMOS transistor P3 is turned on, and the NMOS transistor N5 is turned off. The PMOS transistors P1 and P2 are turned on. That is, the current mirror circuit starts operating, whereby the constant-voltage generating circuit assumes its steady state. Then, the NMOS transistor N1 functions as a constant-current source, and the bias voltage Vbias changes to 1.7 V. The bias voltage Vbias no longer depends on the power-supply voltage Vdd. In other words, the circuit keeps generating a constant bias voltage of 1.7 V.
When the control signal SW falls to "L" level, the PMOS transistor P3 and the NMOS transistor N7 are turned off and the NMOS transistor N5 is turned on, as indicated above. The bias voltage Vbias therefore changes to the power-supply voltage Vdd.
The constant-voltage generating circuit shown in FIG. 2 may be incorporated in an EPROM, along with an equalizing circuit. The equalizing circuit short-circuits any selected bit line to the dummy bit line at prescribed time, equalizing the potentials of the bit line and the dummy bit line. This makes it possible to increase the speed at which data is read from the EPROM.
Furthermore, the EPROM may have an enhancement-type NMOS transistor connected between the Vdd node and the column selecting switch, for charging the bit lines, and an enhancement-type NMOS transistor connected between the Vdd node and a dummy column selecting switch, for charging the dummy bit line. In this case, the output voltage of the constant-voltage generating circuit (FIG. 2) may be supplied to the gates of both enhancement-type NMOS transistors.
The constant-voltage generating circuit shown in FIGS. 1 and 2 can assume two stable states. It assumes the first stable state while the NMOS transistor N1 and the PMOS transistor P2 are on, Vo=2 Vtn. It assumes the second stable state when Vo&lt;Vtn, and V1&gt;Vdd Vtp while I1=I2=0 (at the start of the circuit), where Vtn and Vtp are the threshold voltages of the transistors N1 and P2, respectively. That is, the circuit operates stably when Vo=0 V and, therefore both transistors N1 and P2 are off.
Needless to say, it is demanded that the constant-voltage generating circuit should remain in the first stable state as long as possible. To meet this demand, the bias voltage for the circuit is set at such a value that the voltages Vo and V1 are Vdd and 0 V, respectively (i.e., Vo=Vdd, V1=0 V), at the start of the circuit. More precisely, while the circuit remains in inactive state (that is, while the EPROM remains unselected), the control signal SW is at "L" level, the output signal of the inverter circuit IV is at "H" level, whereby the transistors N5, P2 and N7 remain on, on and off, respectively. When the control signal SW rises to "H" level to activate the circuit, the voltage Vo changes from Vdd toward 2 Vtn. When the circuit is activated, the bit-line potential VBL changes to Vo-Vtp.
If the voltage Vo (=Vdd) rises above 2 Vtn while the circuit remains inactive, the selected bit line will be excessively charged immediately after the circuit is activated. The voltage Vo (i.e., the bit-line potential VBL) momentarily remains at a value greater than 2 Vtn (Vo&gt;2 Vtn) in terms of AC, though it is 2 Vtn in terms of DC while the circuit remains in the first stable state. Namely, the bit-line potential VBL momentarily rises above the value (Vo-Vtn-.alpha.), becoming excessively high, as will be explained in detail with reference to FIG. 4.
FIG. 4 is a timing chart illustrating how the bit-line potential VBL changes with time right after the constant-voltage generating circuit is activated. As may be understood from FIG. 4, the selected bit line is likely to be charged too much it the time the output voltage of the circuit needs a longer time to become stable than the time required to charge the bit line fully.
If the selected bit line will be excessively charged, the following two problems will arise:
(1) Soft Writing of Data
As mentioned above, the constant-voltage generating circuit is designed to clamp the bit-line potential below a predetermined value in order inhibit soft writing of data. If the bit line is excessively charged, however, the bit-line potential will become too high, causing erroneous writing of data into the selected memory cell.
(2) Reduction of Data-Reading Speed
Once the bit line is charged excessively, it takes much time to discharge the bit line to read data from the memory cell. In other words, the access time of the EPROM, i.e., the data-reading time, inevitably become longer.
As described above, the output voltage Vo (=Vdd) of the conventional constant-voltage generating circuit is higher than 2 Vtn while the circuit remains inactive. Immediately after the circuit is activated, the bit line is charged to excess. Consequently, either soft-writing of data or a decrease in the data-reading speed will occur.